1. Field of the Invention
The present invention relates to the manufacturing of integrated circuits and more specifically to the manufacturing of a PNP-type bipolar transistor of optimized characteristics or the simultaneous manufacturing of an NPN-type bipolar transistor and of a PNP-type bipolar transistor both having optimized characteristics. The present invention is especially compatible with complementary MOS-type (CMOS) components manufacturing techniques or techniques in which components of bipolar type and MOS type-components are simultaneously made in a same semiconductor substrate (BICMOS).
2. Discussion of the Related Art
In particular, for bipolar transistors to be adapted to operating at high frequency, their stray capacitances and internal resistances, and especially the collector resistance, have to be minimized.
FIG. 1 shows a conventional structure associating an NPN-type bipolar transistor and a PNP-type bipolar transistor. The NPN transistor is shown on the left-hand side of the drawing and the PNP transistor is shown on the right-hand side. The structure is formed based on a semiconductor single-crystal silicon P-type substrate 1. In this substrate, various implantations have been performed. An N+-type implantation is intended for forming a region 2 corresponding to the buried collector of the NPN transistor. On the side of the PNP transistor, an N-type implantation is used to define an insulation area of this transistor and a P+-type implantation is intended for forming a buried collector area 4. A P+-type insulation implantation 6 is formed at the periphery of the NPN transistor, this implantation being preferably performed at the same time as that intended for forming collector 4 of the PNP transistor. An N+-type implantation 7 is formed at the periphery of the PNP transistor, this implantation being preferably performed at the same time as the collector implantation of the NPN transistor.
After this, an epitaxy step has been performed to obtain a lightly-doped layer over the entire surface of the device. After processing, this layer is N-type doped on the side of the NPN transistor (reference 10) to form its collector and is P-type doped (reference 11) on the side of the PNP transistor to form its collector. It is preferably N-type doped at the periphery of the PNP transistor to contribute to its insulation. On the NPN transistor side, a P-type base region 12 and an N-type emitter region 13 have been formed in epitaxial layer 10, for example by diffusion from a polysilicon area 14. A collector well 16 is in contact with buried layer 2. On the PNP transistor side, an N-type base region 18 in which an emitter region 19 is formed, for example by diffusion from a P-type doped polysilicon area 20, has been formed in P-type region 11. Just as for the NPN transistor, a P-type collector well 22 contacts collector buried layer 4.
Various elements of the components of FIG. 1 have not been described, especially the field insulation and contacting areas. These are indeed conventional elements within the abilities of those skilled in the art, which can refer to usual works on semiconductors or to publications of STMicroelectronics Company.
FIGS. 2A, 2B, and 2C show curves of concentration in atoms per cm3 as a function of distance d. FIG. 2A corresponds to cross-section plane AA taken depthwise on the side of the NPN transistor, FIG. 2B corresponds to cross-section plane BB depthwise on the side of the PNP transistor, and FIG. 2C corresponds to cross-section plane CC in the transverse direction from the collector buried layer of the NPN transistor to the collector buried layer of the PNP transistor. In these drawings, the reference of the corresponding curve has been represented for each curve portion.
These curves will be described to show the compromises with which those skilled in the art are confronted to simultaneously optimize the performances of the NPN and PNP transistors.
As shown in FIG. 2A, the collector of the NPN transistor corresponds to region 10, which is a portion of an epitaxial layer, possibly appropriately overdoped, and to a region 2 which corresponds to a buried layer and which is used to take the collector contact vertically via collector well 16. To optimize the operation of the NPN transistor, the thickness corresponding to layer portion 10 must be carefully chosen. This thickness, which is not very different from the thickness of the epitaxial layer, must not be too small, so that the transistor can have a satisfactory breakdown voltage. It must, however, be as small as possible to enable the transistor to operate at a high frequency.
Now considering the PNP transistor, in relation with FIG. 2B, several delicate compromises have to be made. In particular, the doping of insulating layer 3 must be sufficiently large. Given that the dopants of layers 3 and 4 interpenetrate, a relatively high implantation level has to be chosen for P layer 4, to have a sufficiently high final P-type doping of region 4. This increase of the doping level of buried layer 4 results in a compensation of the N doping of region 3, and this problem is difficult to solve. Further, buried layer 4 tends to rise higher in epitaxial layer 11. To have a sufficient remaining lightly-doped collector region 11 after the various thermal processings, an epitaxial layer thicker than what would be desired for the previously-described NPN transistor optimization has to be chosen.
Referring to FIG. 2C, it should be noted that in fact, at the level of the shown cross-section, the doping level of insulating region 6 will be higher than the doping level of buried layer 4. Indeed, as previously indicated, the characteristics of buried layer 4 result from a compensation between the desired P-type doping and the N-type doping of insulating layer 3. Thus, region 6 is very heavily doped, more than what would be desired, and this increases the lateral stray capacitance between buried collector 2 of the NPN transistor and insulation layer 6, which is at the substrate potential. Thus, the collector/substrate capacitance of the NPN transistor increases, which adversely affects its operating speed and its power consumption. To avoid the various problems due to these stray capacitances, it will be understood by considering FIG. 2C that the implantations have to be spaced apart from one another, which results in buried layers 2, 6, 7, and 4. This results in an increase of the surface area occupied by the components.
Compromises thus inevitably have to be made, as indicated previously, as for the choice of the thickness of epitaxial layer 10-11, for the choice of the doping level of the P-type buried layers, and for the choice of the doping level of insulating layer 3. Compromises thus have to be made, especially between the optimization of the NPN transistor and the PNP transistor optimization.